Seonjin Na

School of Computer Science. Georgia Tech.

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I am currently a Postdoctoral Researcher in HPArch Group at Georgia Institute of Technology (Georgia Tech) supervised by Prof. Hyesoon Kim. Prior to Georgia tech, I received a Ph.D in School of Computing from KAIST (2023), advised by Prof. Jaehyuk Huh.

My research interests lie in GPU architecture, trusted computing, heterogeneous systems, distributed computing, and systems for machine learning. During my Ph.D. studies, I focused on building secure architecture to provide a trusted execution environment(TEE) on accelerators such as GPUs, and NPUs with low-performance overhead. Currently, I am actively engaged in extending my research field to address various challenges in the multi-GPU architecture, security, and accelerating large language models.

News

May 30, 2024 Out paper Allegro: GPU Simulation Acceleration for Machine Learning Workloads has been accepted at MLArchSys!
Apr 30, 2024 I will serve as Artifact Evaluation Committee for OSDI 2024 / ATC 2024 !
Apr 01, 2024 I will serve as Program Committee for SC 2024!
Mar 20, 2024 Our paper Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs has been accepted at ISCA-2024!
Feb 23, 2024 I will serve as Artifact Evaluation Committee for ISCA 2024!
Feb 22, 2024 I will attend GPGPU 2024 workshop as a moderator!
Oct 24, 2023 Our paper Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management has been accepted at HPCA-2024!
Jul 24, 2023 Our paper Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training has been accepted at MICRO-2023!
Dec 13, 2022 I will be joining the HPArch group as a postdoctoral researcher.
Dec 09, 2022 I defended my Ph.D. thesis and submitted my dissertation!
Aug 23, 2022 Our paper Tunable Memory Protection for Secure NPUs has been accepted at ICCD-2022!
Oct 28, 2021 Our paper TNPU has been accepted at HPCA-2022!
Oct 28, 2020 Our paper Common Counters has been accepted at HPCA-2021!

Publications

  1. MLArchSys
    Allegro: GPU Simulation Acceleration for Machine Learning Workloads
    Euijun Chung, Seonjin Na, and Hyesoon Kim
    In 2024 MLArchSys in ISCA , 2024
  2. ISCA
    Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs
    Yuan Feng, Seonjin Na, Hyesoon Kim, and Hyeran Jeon
    In 2024 IEEE International Symposium on Computer Architecture (ISCA) , 2024
  3. HPCA
    Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management
    Seonjin Na, Jungwoo Kim, Sunho Lee, and Jaehyuk Huh
    In 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2024
  4. MICRO
    Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
    Jungwoo Kim, Seonjin Na, Sanghyeon Lee, Sunho Lee, and Jaehyuk Huh
    In 2023 IEEE/ACM International Symposium on Microarchitecture (MICRO) , 2023
  5. ICCD
    Tunable Memory Protection for Secure Neural Processing Units
    Sunho Lee, Seonjin Na, Jungwoo Kim, Jongse Park, and Jaehuyk Huh
    In 2022 IEEE International Conference on Computer Design (ICCD) , 2022
  6. HPCA
    TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit
    Sunho Lee, Jungwoo Kim, Seonjin Na, Jongse Park, and Jaehuyk Huh
    In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2022
  7. HPCA
    Common Counters: Compressed Encryption Counters for Secure GPU Memory
    Seonjin Na, Sunho Lee, Yeonjae Kim, Jongse Park, and Jaehyuk Huh
    In 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2021