Publications

publications by categories in reversed chronological order. generated by jekyll-scholar.

2026

  1. TechReport
    Nemotron 3 Super: Open, Efficient Mixture-of-Experts Hybrid Mamba-Transformer Model for Agentic Reasoning
    2026
    PDF
  2. arXiv
    CuFuzz: Hardening CUDA Programs through Transformation and Fuzzing
    Saurabh Singh, Ruobing Han, Jaewon Lee, Seonjin Na, Yonghae Kim, Taesoo Kim, and Hyesoon Kim
    2026
    arXiv

2025

  1. MICRO
    Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering
    Euijun Chung, Seonjin Na, Sung Ha Kang, and Hyesoon Kim
    In IEEE/ACM International Symposium on Microarchitecture (MICRO) , 2025
    PDF Slides
  2. CAL
    Contention-Aware GPU Thread Block Scheduler for Efficient GPU-SSD
    Xueyang Liu, Seonjin Na, Euijun Chung, Jiashen Cao, Jing Yang, and Hyesoon Kim
    In IEEE Computer Architecture Letters (CAL) , 2025
    PDF
  3. ISCA
    Unified Memory Protection with Multi-granular MAC and Integrity Tree for Heterogeneous Processors
    Sunho Lee, Seonjin Na, Jeongwon Choi, Jinwon Pyo, and Jaehyuk Huh
    In IEEE International Symposium on Computer Architecture (ISCA) , 2025
    PDF Slides
  4. MLSys
    FlexInfer: Flexible LLM Inference with CPU Computations
    Seonjin Na, Geonhwa Jeong,  Byunghoon Ahn, Aaron Jezghani, Jeffrey Young, Christopher J. Hughes, Tushar Krishna, and Hyesoon Kim
    In Conference on Machine Learning and Systems (MLSys) , 2025
    PDF Slides
  5. HPCA
    Let-Me-In: (Still) Employing In-pointer Bounds metadata for Fine-grained GPU Memory Safety
    Jaewon Lee, Euijun Chung,  Saurabh Singh, Seonjin Na, Yonghae Kim, Jaekyu Lee, and Hyesoon Kim
    In IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2025
    PDF Slides

2024

  1. IISWC
    Understanding Performance Implications of LLM Inference on CPUs
    Seonjin Na, Geonhwa Jeong,  Byunghoon Ahn, Jeffrey Young, Tushar Krishna, and Hyesoon Kim
    In IEEE International Symposium on Workload Characterization (IISWC) , 2024
    PDF Slides
  2. MLArchSys
    Allegro: GPU Simulation Acceleration for Machine Learning Workloads
    Euijun Chung, Seonjin Na, and Hyesoon Kim
    In MLArchSys in ISCA , 2024
    PDF Slides
  3. ISCA
    Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs
    Yuan Feng, Seonjin Na, Hyesoon Kim, and Hyeran Jeon
    In IEEE International Symposium on Computer Architecture (ISCA) , 2024
    PDF Slides
  4. HPCA
    Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management
    Seonjin Na, Jungwoo Kim, Sunho Lee, and Jaehyuk Huh
    In IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2024
    PDF Slides

2023

  1. MICRO
    Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
    Jungwoo Kim, Seonjin Na, Sanghyeon Lee, Sunho Lee, and Jaehyuk Huh
    In IEEE/ACM International Symposium on Microarchitecture (MICRO) , 2023
    PDF Slides

2022

  1. ICCD
    Tunable Memory Protection for Secure Neural Processing Units
    Sunho Lee, Seonjin Na, Jungwoo Kim, Jongse Park, and Jaehyuk Huh
    In IEEE International Conference on Computer Design (ICCD) , 2022
    PDF Slides
  2. HPCA
    TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit
    Sunho Lee, Jungwoo Kim, Seonjin Na, Jongse Park, and Jaehyuk Huh
    In IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2022
    PDF Slides

2021

  1. HPCA
    Common Counters: Compressed Encryption Counters for Secure GPU Memory
    Seonjin Na, Sunho Lee, Yeonjae Kim, Jongse Park, and Jaehyuk Huh
    In IEEE International Symposium on High-Performance Computer Architecture (HPCA) , 2021
    PDF Slides