Seonjin Na
School of Computer Science. Georgia Tech.
I am currently a Postdoctoral Fellow in HPArch Group at Georgia Institute of Technology (Georgia Tech) supervised by Prof. Hyesoon Kim. Prior to Georgia tech, I received a Ph.D in School of Computing from KAIST (2023), advised by Prof. Jaehyuk Huh.
My research interests lie in GPU architecture, trusted computing, heterogeneous systems, distributed computing, and systems for machine learning. During my Ph.D. studies, I focused on building secure architecture to provide a trusted execution environment(TEE) on accelerators such as GPUs, and NPUs with low-performance overhead. Currently, I am actively engaged in extending my research field to address various challenges in the multi-GPU architecture, hardware security, and accelerating large language models (LLMs).
Research Interest (Keyword): GPU/NPU Architecture, Secure Architecture for GPU/NPU, Systems for Machine Learning.
I am currently looking for full-time job opportunities in industry.
News
| Nov 02, 2024 | Our paper has been accepeted at HPCA 2025. |
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| Oct 01, 2024 | I have been selected as one of the presenters for the MICRO 2024 PhD Forum. |
| Sep 06, 2024 | I will serve as Program Committee for IPDPS 2025. |
| Aug 16, 2024 | I will serve as Artifact Evaluation Committee for MICRO 2024. |
| Jul 24, 2024 | I will serve as Artifact Evalution Committee for EuroSys 2025. |
| Jul 17, 2024 | Our paper, Understanding Performance Implications of LLM Inference on CPUs, has been accepted at IISWC 2024. |
| Jul 13, 2024 | I will serve as Travel Grants Co-Chairs for ASPLOS 2025. |
| Jul 02, 2024 | I will serve as Artifact Evaluation Committee for ASPLOS 2025. |
| May 30, 2024 | Our paper, Allegro: GPU Simulation Acceleration for Machine Learning Workloads, has been accepted at MLArchsys. |
| Apr 30, 2024 | I will serve as Artifact Evaluation Committee for OSDI 2024 / ATC 2024. |
| Apr 01, 2024 | I will serve as Program Committee for SC 2024. |
| Mar 20, 2024 | Our paper, Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs, has been accepted at ISCA 2024. |
| Feb 23, 2024 | I will serve as Artifact Evaluation Committee for ISCA 2024. |
| Feb 22, 2024 | I will attend GPGPU 2024 workshop as a moderator. |
| Oct 24, 2023 | Our paper, Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management, has been accepted at HPCA 2024. |
| Jul 24, 2023 | Our paper, Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training , has been accepted at MICRO 2023. |
| Dec 13, 2022 | I will be joining the HPArch group as a postdoctoral researcher. |
| Dec 09, 2022 | I defended my Ph.D. thesis and submitted my dissertation. |
| Aug 23, 2022 | Our paper, Tunable Memory Protection for Secure NPUs , has been accepted at ICCD 2022. |
| Oct 28, 2021 | Our paper, TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit, has been accepted at HPCA 2022. |
| Oct 28, 2020 | Our paper, Common Counters: Compressed Encryption Counters for Secure GPU Memory, has been accepted at HPCA 2021. |